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BL22P64 specification 8 - b i t o t p mcu v 1 . 3 shanghai belling co., ltd.
tel86-21-64850700 web: www.belling.com.cn page 2 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 1 product overview BL22P64 can be used for dedicated control functions in a variety of applications, such as induction cooker, microwave oven, soybean milk maker and so o n. a dual address/data bus architecture and bit-config urable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counter, a/d converter and pwm are designed for measure and control. 2 features 8-bit cisc core compatible with motorola hc05 4k byte otp rom 208 byte ram three configurable i/o ports (18 pins) one 8-bit pwm output one 8-bit timer/counter with time interval mode a/d converter with nine input channels and 10-bit r esolution four interrupt sources (two external interrupt, tim er interval interrupt, pwm interrupt) watch dog 3v lvr four configurable clock circuit: crystal/ceramic oscillator (400k-4mhz) external rc oscillator 3.2mhz(vdd=5v) internal rc oscillator 0.5mhz(vdd=5v) internal rc oscillator operating voltage: 2.7-5.5v operating temperature: -40-85 package types: sop20/dip20/sop16 4kv emc 3 pin assignments sop20/dip20
tel86-21-64850700 web: www.belling.com.cn page 3 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 4 pin descriptions pin name in/out pin description share description gnd - ground - p10 i/o xin p11 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors or pull-down resistors are assignable by software. xout p12 in schmitt trigger input port reset/vpp p20 i/o t0 p21 i/o - p22 i/o - p23 i/o - p24 i/o - p25 i/o - p26 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors are assignable by software. adc8/clo p00 i/o adc0/int0 p01 i/o adc1/int1 p02 i/o adc2 p03 i/o adc3 p04 i/o adc4 p05 i/o adc5 p06 i/o adc6/pwm p07 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. adc7 vdd - voltage input - 5 function descriptions 5.1 block diagram
tel86-21-64850700 web: www.belling.com.cn page 4 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 208b ram port i/o and periphery control hc05 cpu port 0 port 1 port 2 osc basic timer timer 0 adc pwm p00/adc0/int0 p01/adc1/int1 p02/adc2 p03/adc3 p04/adc4 p05/adc5 p06/adc6/pwm p07/adc7 p10 p11 p12 p20/t0 p21 p22 p23 p24 p25 p26/adc8/clo xin xout 4kb rom block diagram 5.2 address spaces $0000-$002f: control registers $0030-$00ff: ram (208 bytes) $0100-$0fff: reserved $1000-$1fff: otp rom (4096 bytes) 5.3 control registers control registers register name address r/w reset value t0cnt $00 r 0000 0000 t0data $01 r/w 1111 1111 t0con $02 r/w 00-- 0-00 mcr $03 r/w ---- ---r btcon $0c r/w 0000 1000 btcnt $0d r 0000 0000 p0 $10 r/w 0000 0000 p1 $11 r/w ---- -000 p2 $12 r/w -000 0000 p0conh $16 r/w 0000 0000 p0conl $17 r/w 0000 0000 p0pnd $18 r/w ---- 0000 p1con $19 r/w 00-- 0000 p2conh $1a r/w -000 0000 p2conl $1b r/w 0000 0000 pwmdata $22 r/w 0000 0000 pwmcon $23 r/w 00-0 0000 adcon $27 r/w 0000 1000
tel86-21-64850700 web: www.belling.com.cn page 5 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. addatah $28 r xxxx xxxx addatal $29 r ---- --xx note: ? ?? ? - : not used; x: undefined; r: determined by opbit[2] ? ?? ? 5.3.1 t0cnt timer 0 counter register t0cnt is a 8-bit counter register of timer 0. t0cnt is read only. 5.3.2 t0data timer 0 data register t0data is a 8-bit data register to set match data o f timer 0. when the counter value is identical to the value written to t0data, generates a timer 0 ma tch interrupt. 5.3.3 t0con timer 0 control register timer 0 control register, is used to select the tim er 0 operating mode. .7-.6 t0ps[1:0] timer 0 input clock selection 00: fsys/4096 01: fsys/256 10: fsys/8 11: fsys note fsys is system frequency which is half of oscillato rs .5-.4 not used .3 t0clr timer 0 counter clear bit. value is 0 w hen read. 0: no effect 1: clear the timer 0 counter (when write) 0 .2 not used .1 t0e timer 0 interrupt enable bit 0: disable t0 interrupt 1: enable t0 interrupt .0 t0f timer 0 interrupt pending bit 0: no t0 interrupt pending (when read) 0: clear t0 pending bit (when write) 1: interrupt is pending (when read) 1: no effect (when write) 5.3.4 mcr miscellaneous control register mcr is used to control lvr. the reset value is dete rmined by opbit[2] .7-.1 not used .0 lvre lvr enable bit 0: lvr disable 1: lvr enable 5.3.5 btcon basic timer control register btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to control the watchdog timer. .7-.4 wdte[3:0] watchdog timer enable bits
tel86-21-64850700 web: www.belling.com.cn page 6 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 1010: disable watchdog function other value: enable watchdog function note watchdog function is enable when reset. .3-.2 btps[1:0] basic timer input clock selection bits 00: fsys/4096 01: fsys/1024 10: fsys/256 11: fsys/128 .1 btclr basic timer counter clear bits. value is 0 when read. 0: no effect 1: clear basic timer counter .0 dvclr divider clear bit for basic timer and tim er 0. value is 0 when read. 0: no effect 1: clear both dividers 5.3.6 btcnt basic timer counter btcnt is a 8-bit basic timer counter, and read only . btcnt can be cleared by writing a "1" to btclr (btcon.1). 5.3.7 p0 port 0 data register p0 is data register for port 0. 5 55 5.3.8 .3.8 .3.8 .3.8 p1 port 1 data register p1 is data register for port 1. 5 55 5.3.9 .3.9 .3.9 .3.9 p2 port 2 data register p2 is data register for port 2. 5.3.10 p0conh port 0 control register (high byte) .7-.6 p07c[1:0] p07 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: a/d converter input (adc7) .5-.4 p06c[1:0] p06 configuration bits 00: schmitt trigger input; pull-up enable 01: pwm output 10: push-pull output 11: a/d converter input (adc6) .3-.2 p05c[1:0] p05 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: a/d converter input (adc5) .1-.0 p04c[1:0] p04 configuration bits
tel86-21-64850700 web: www.belling.com.cn page 7 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: a/d converter input (adc4) 5.3.11 p0conl port 0 control register (low byte) .7-.6 p03c[1:0] p03 configuration bits 00: schmitt trigger input 01: schmitt trigger input; pull-up enable 10: push-pull output 11: a/d converter input (adc3) .5-.4 p02c[1:0] p02 configuration bits 00: schmitt trigger input 01: schmitt trigger input; pull-up enable 10: push-pull output 11: a/d converter input (adc2) .3-.2 p01c[1:0] p01 configuration bits 00: schmitt trigger input / int1 input 01: schmitt trigger input; pull-up enable / int1 input 10: push-pull output 11: a/d converter input (adc1) .1-.0 p00c[1:0] p00 configuration bits 00: schmitt trigger input / int0 input 01: schmitt trigger input; pull-up enable / int0 input 10: push-pull output 11: a/d converter input (adc0) 5.3.12 p0pnd port 0 interrupt pending register .7-.4 not used .3 int1e int1 interrupt enable bit 0: int1 disable 1: int1 enable .2 int1f int1 pending bit 0: no interrupt pending (when read) 0: pending bit clear (when write) 1: interrupt is pending (when read) 1: no effect (when write) .1 int0e int0 interrupt enable bit 0: int0 disable 1: int0 enable .0 int0f int0 pending bit 0: no interrupt pending (when read) 0: pending bit clear (when write) 1: interrupt is pending (when read) 1: no effect (when write)
tel86-21-64850700 web: www.belling.com.cn page 8 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 5.3.13 p1con port 1 control register .7 p11od p11 open-drain enable bit 0: p11 as a push-pull output 1: p11 as a n-channel open-drain output .6 p10od p10 open-drain enable bit 0: p11 as a push-pull output 1: p11 as a n-channel open-drain output .5-.4 not used .3-.2 p11c[1:0] p11 configuration bits 00: schmitt trigger input 01: schmitt trigger input; pull-up enable 10: push-pull output 11: schmitt trigger input; pull-down enable .1-.0 p10c[1:0] p10 configuration bit 00: schmitt trigger input 01: schmitt trigger input; pull-up enable 10: push-pull output 11: schmitt trigger input; pull-down enable note when system clock comes from crystal/ceramic oscill ator or external rc oscillator, p10 and p11 must be set as input and pull-up disable 5.3.14 p2conh port 2 control register (high byte) .7 not used .6-.4 p26c[2:0] p26 configuration bits 000: schmitt trigger input; pull-up enable 001: schmitt trigger input 01x: a/d converter input (adc8) 100: open-drain output 101: open-drain output; pull-up enable 110: open-drain output 111: clo output .3-.2 p25c[1:0] p25 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: open-drain output .1-.0 p24c[1:0] p24 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: open-drain output 5.3.15 p2conl port 2 control register (low byte) .7-.6 p23c[2:0] p23 configuration bits
tel86-21-64850700 web: www.belling.com.cn page 9 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: open-drain output .5-.4 p22c[2:0] p22 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: open-drain output .3-.2 p21c[1:0] p21 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: open-drain output .1-.0 p20c[1:0] p20 configuration bits 00: schmitt trigger input; pull-up enable 01: schmitt trigger input 10: push-pull output 11: t0 match output 5.3.16 pwmdata pwm data register pwmdata determines the duty of output clock generat ed by 8-bit pwm circuit. 5.3.17 pwmcon pwm control register .7-.6 pwmps[1:0] pwm input clock selection bits 00: fsys/64 01: fsys/8 10: fsys/2 11: fsys .5 not used .4 pwmdrs pwmdata reload interval selection bit 0: reload from 8-bit up counter overflow 1: reload from 6-bit up counter overflow .3 pwmclr pwm counter clear bit. value is 0 when read. 0: no effect 1: clear the pwm counter (when write) .2 pwmce pwm counter enable bit 0: stop counter 1: start (resume countering) .1 pwmie pwm overflow interrupt enable bit (8-bit overflow) 0: disable interrupt 1: enable interrupt .0 pwmif pwm overflow interrupt pending bit 0: no interrupt pending (when read) 0: clear pending bit (when write)
tel86-21-64850700 web: www.belling.com.cn page 10 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 1: interrupt is pending (when read) 1: no effect (when write) 5.3.18 adcon a/d control register .7-.4 adch[3:0] a/d input pin selection bits 0000: adc0 0001: adc1 0010: adc2 0011: adc3 0100: adc4 0101: adc5 0110: adc6 0111: adc7 1000: adc8 1001: gnd (for test) 1010: gnd (for test) 1011: gnd (for test) 1100: gnd (for test) 1101: vdd (for test) 1110: vdd/4 (for test) 1111: vdd/2 (for test) .3 eoc a/d end-of-conversion status bit read only 0: a/d conversion is in progress 1: a/d conversion complete .2-.1 adps[1:0] clock source selection bit 00: fsys/8 01: fsys/4 10: fsys/2 11: fsys .0 adce conversion start bit. value is 0 when re ad. 0: no meaning 1: a/d conversion start 5.3.19 addatah a/d data register(high 8-bit) 5.3.20 addatal a/d data register(low 2-bit) addatah and addatal are used to storage conversion data of a/d. 5.4 opbit opbit is a special byte in otp rom and used to conf igure some initial functions for BL22P64. opbit is set when otp written. .7 encr 0: otp read protection 1: otp can be read .3 p12f
tel86-21-64850700 web: www.belling.com.cn page 11 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 0: p12 as normal i/o pin 1: p12 as external reset input pin .2 lvreo 0: lvr disable 1: lvr enable .0-.1 osc/rc 00: crystal/ceramic oscillator (400k-4mhz) as syst em clock 01: external rc oscillator as system clock 10: internal rc oscillator(0.5mhz) as system clo ck 11: internal rc oscillator(3.2mhz) as system clock 6 electrical data 6.1 absolute maximum ratings (t a =25 ) parameter symbol condition rating unit supply voltage v dd - -0.3 to +6.5 v input voltage v i all ports -0.3 to vdd+0.5 v output voltage v o all ouput ports -0.3 to vdd+0.5 v output current high i oh one i/o pin active -25 ma all i/o pin active -80 ma output current low i ol one i/o pin active +30 ma all i/o pin active +150 ma operating temperature t a - -40 to +85 storage temperature t stg - -65 to +150 6.2 dc electrical characteristics (t a =25 vdd=2.7-5.5v) parameter sym. condition min typ max unit input high voltage v ih p0,p1,p2 vdd=2.7-5.5v 0.8vdd - vdd v input low voltage v il p0,p1,p2 vdd=2.7-5.5v 0 - 0.2vdd v output high voltage v oh i oh =-10ma p0,p1,p2 vdd=4.5-5.5v vdd-1.5 vdd-0.4 - v output low voltage v ol i ol =25ma p0,p1,p2 vdd=4.5-5.5v - 0.5 2.0 v input high leakage current i ih all input v in =vdd - - 1 ua input low leakage current i il all input v in =0 - - 1 ua
tel86-21-64850700 web: www.belling.com.cn page 12 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. pull-up resistors r pu p0,p1,p2 vdd=2.7-5.5v 15 30 100 k pull-down resistors r pd p0,p1,p2 vdd=2.7-5.5v 15 30 100 k dynamic working current i dd 4mhz clock vdd=4.5-5.5v - 5 10 ma i std1 stop mode lvr disable vdd=4.5-5.5v - 0.1 1 standby working current i std2 stop mode lvr enable vdd=4.5-5.5v - 10 20 ua 6.3 lvr characteristics (t a =25 vdd=2.7-5.5v) parameter sym. condition min typ max unit low voltage reset v lvr - 2.7 3.0 3.3 v 6.4 a/d converter characteristics ( t a =25 vdd=5.0v) parameter sym. condition min typ max unit total accracy - vdd=5v fosc=4mhz - - 3 lsb integral linearity error ile vdd=5v fosc=4mhz - - 2 lsb differential linearity error dle vdd=5v fosc=4mhz - - 1 lsb offset error of top eot vdd=5v fosc=4mhz - 1 3 lsb offset error of bottom eob vdd=5v fosc=4mhz conversion time t con vdd=5v fosc=4mhz - 25 - us analog input voltage v ian - vss - vdd v analog input impedance r an - 2 - - m analog input current i adin vdd=5v - - 10 ua vdd=5v - 1 3 ma analog block current i adc vdd=5v power down mode - 0.1 0.5 ua
tel86-21-64850700 web: www.belling.com.cn page 13 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. 7. package dimensions dip20
tel86-21-64850700 web: www.belling.com.cn page 14 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. sop20
tel86-21-64850700 web: www.belling.com.cn page 15 of 15 b bb bl ll l22p64 22p64 22p64 22p64 spec spec spec specification ification ification ification ? ? ? ? ? ? ? ? ?? ?? ?? ?? shanghai belling co., ltd. sop16 150mil dimensions in mil dimensions in milimeter symbol max. nom. min. max. nom. min. a 238 - 244 6.05 - 6.20 b 150 - 157 3.80 - 4.00 c 14 - 19 0.36 - 0.48 c' 386 - 398 9.80 - 10.10 d 53 - 62 1.35 - 1.57 e - 50 - - 1.27 - f 4 - - 0.10 - - g 22 - 32 0.56 - 0.82 h 4 - 12 0.10 - 0.30 0 - 8 0 - 8

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